The transformation by artificial intelligence is relentless, and there will be before and after Co-Packaged Optics became a cornerstone technology for it in the semiconductor landscape. Co-Packaged Optics (CPO) emerged as a key solution to the bandwidth, thermal and performance challenges of AI at the OCP APAC 2025 Summit in Taipei ASE Inc. spotlighted CPO
Over two days, ASE Executive Vice President Yin Chang and Charles Lee Director of Engineering—got up on stage to drive home the point that Co-Packaged Optics is going to revolutionize data infrastructure. Both set out ASE’s autoprofessed roadmap on tightly integrating Co-Packaged Optics with advanced packaging to serve the market growing at lightening pace from AI applications.
AI Acceleration Outpaces Traditional Scaling
Yin Chang warned in a keynote on August 5, 2025 that chip scaling as it has been done for the past 50 years would be insufficient for the AI era. Global AI economy is expected to grow from $Renicae2 billion in 2023 to around $Neuro2 trillion by up to 2033, gloomy forecasts suggest. Data generation is expected to top 200ZB by the end of the decade, meaning compute performance will need to multiply up to seven times per year.
Chang said that this expansion is nearing the limits of existing packaging, memory bandwidth, and thermal handling. Co-Packaged Optics takes that a step further – here, instead of connecting electrical signals to the ASIC and photonic engines with metal traces as we do at current, Co-packaging technology embeds photonic engines directly inside computer chip packages, converting those batch-processed bundled connections into light with orders-of-magnitude lower latencies and power consumption.
Co-Packaged Optics is being implemented by ASE to build the fans for next-gen and highly scalable DCs. The Co-Packaged Option solutions are underway with fan-out based 3D ICs, laser diode integration, edge coupling, etc. The company is working with silicon vendors to solve thermal issues through a combination of solutions, including micro-channel cooling and tin-based materials that are needed as GPUs approach 1,500W by 2030.
CPO Unlocks 32x Performance Gains
Charles Lee double down on the case for Co-Packaged Optics — August 6, 2025 Today’s 2.5D/3D IC packaging technologies can realize up to a 10X performance boost, he continued, but CPO-based solutions could push that up to 32X — and at much lower power consumption.
Co-Packaged Optics is at the heart of ASE’s advanced packaging portfolio, as Lee demonstrated. Fan-Out Chip on Substrate (FOCoS), Substrate-Like PCBs (SLP), and ASE’s VIPack have all introduced Co-Packaged Optics to enhance these technologies. This change represents a shift to what ASE refers to as “all-in-one optics.
He then showed data that illustrates how packaging is not just a post-design step, but actually drives system performance:
- Nvidia GP200 Cluster: 22x better PPF / CPO (Competition-sponsored performance per watt) generated by the packaging, or 25x better CPE (competition-sponsored processor efficiency), allowed system to fit in a single rack instead of 25 racks.
- Reporter,Size Reduction: Co-Packaged Optics enable up to a 70% reduction in system size through 2.5D and 3D IC%%%% integration.
- Assembly Efficiency: Panel-level packaging with CPO drives up yield and lowers unit cost.
Collaboration Becomes Mission-Critical
Chang and Lee both said Co-Packaged Optics will only work if there is strong ecosystem-wide cooperation. Packaging can no longer be thought of as an afterthought, is how Chang put it. AI system performance is now central to it.
ASE made its mark by targeting USI, which was particularly well-regarded for merging advanced packaging capabilities with electronic manufacturing services. This will allow ASE to bring complete end-to-end solutions (Design to Deployment) including Co-Packaged Optics.
Now, AI is transforming — or has already transformed — everything from the way architecture works to how we approach thermal design Co-Packaged Optics is now a must. A crucial requirement to unleash the performance and efficiency in future AI workloads.
FAQ
CPPI 2020: Co-Packaged Optics integrates optical engines directly in the chip package to eliminate pluggable optics, drive better performance and less power.
AI workloads require orders of magnitude higher bandwidth and performance. CPO provides ways to reduce the latency and the thermal cost of these demands.
CPO solutions offer up to 32x higher performance and improve the energy efficiency of transactions by up to 25 times if ASE is to be believed from traditional packaging methods.
CPO figured out — ASE is a prime driver, with support from silicon vendors and demonstrators like Nvidia GP200 clusters.
In addition, ASE is working on laser diode integration tools, 3D fan-out ICs and another cooling solution for handling the high thermal load of next-generation chips.
