ASE Group Executive Vice President Tingu Yin Chang made a provocative move at the first Open Compute Project (OCP) APAC Summit in Taipei announcing ASE’s co-packaged optics (CPO) program as a competitor to TSMC’s silicon photonics dominance.
With heightened global demand for AI computing, not only the semiconductor industry need to scale up, but also where the co-packaged optics are becoming a battle ground. ASE CPO packaging strategy that packages both optical engines (OEs) and ASICs in a single module is a direct response to TSMC’s COmpact Universal Photonic Engine (COUPE).
Co-package optics innovation from this addresses three challenges directly:
- Growing package sizes
- Soaring power consumption
- Complicated thermal management
ASE is now ramping up its investments in co-packaged optics — it’s the future for AI data centers, it says.
Legacy Packaging Still Holds Ground
Co-packaged optics have made notable progress, however, traditional packaging technologies remain substantially less expensive. Old solutions are still the most cost-effective; they have much more matured production lines, for now.
But the tide is turning. In the next few years, co-packaged optics may establish a new benchmark for how AI systems transmit and compute data.
A $5 Trillion Market Emerges: Co-Packaged Optics and AI
Chang reckons that the AI semiconductor supply chain will surpass $5 trillion in 2033, compared to less than $200 million a few years back. This is primarily fueled with the help of next-gen AI models, such as:
- Multimodal AI systems
- Autonomous AI agents
These systems result in a heavy demand for computational power and memory bandwidth, which drives packaging limits. That’s where co-packaged optics is going to step in.
Memory Bandwidth: A Growing Bottleneck
Every year, AI model performance has multiplied at a rate of 2x to 7x, which means even the highest-bandwidth memory (or HBM) cannot catch up either. Co-packaged optics provides an efficient way to interconnect SoCs and memory in high-density modules to close the gap.
According to ASE, module footprints may scale up to 10 times by 2027, requiring alternative packaging and methods for manufacturing yield.
Scaling Up: Bigger Panels & Lower Temperatures: ASE’s Thermal Edge
ASE is also investing in co-packaged optics:
- Larger panel sizes to improve utilization from 57% to 87% ( 300mm & 600mm )
- Getting temps of 30°C on internal modules, even with 500W power draw for the GPU
Thermal design is a key part of the ASE co-packaged optics plan, which is vital because world air-cooled systems run up against their thermal limits at 50C.
Why Co-Packaged Optics Matters
So all of this is not just innovative, it’s key — the co-packaged optics rise of the AI data centers. ASE and TSMC is only one, but representative race, and all these races will boil down to a only few tasks: breaking the bandwidth and pounding down the power and thermal challenges.
As AI continues to gear up, co-packaged optics are likely to evolve into a pillar of next-generation semiconductor packaging.
FAQs
Co-packaged optics (CPO) is a way to combine optical engines and ASICs into one package, increasing bandwidth, and power efficiency.
Both utilize silicon photonics but ASE’s CPO packages differ in architecture from TSMC’s COOPE engine.
GPUs are now hitting 500W, so heat in dense modules is a challenge to manage. ASE only aims for 30°C internally with its CPO.
At least not more soon, as legacy systems are cheaper but due to performance benefits CPO is predicted to grow at a rapid pace.
